The present invention relates to integrated-circuits and, in particular, to a circuit and method for detecting shorts between adjacent parallel conductors in integrated circuit memories.
In memory arrays where the column lines are parallel to each other and separated by an insulator, one defect arising during manufacture is a short between adjacent column lines. A column-line short may be caused, for example, by an etching process that leaves a filament of conducting material between column lines formed from a single layer of that conducting material, such as doped polycrystalline silicon. It is necessary to test such memory arrays during manufacture to detect the presence or absence of these column-line shorts.
A typical prior-art column-line short detection circuit and method requires a first decoder to couple a selected column line to the sense amplifier and a second decoder to couple the rest of column lines to ground (Vss). All of the wordlines are coupled to low voltage (Vss) during the test. If the sense amplifier indicates no current flow in selected column line, then the selected column line is not shorted to an adjacent column line. However, if the sense amplifier indicates a current flow from the selected column line to an adjacent column line and to ground, then a short exists between the selected column line and an adjacent column line.
The second decoder is complex, requiring a large number of transistors and a large area for layout.
There is a need for a simple circuit and method for detecting shorts between adjacent, parallel conductors in integrated circuit memories.